An Architecture Description Language for Embedded Hardware Platforms

Embedded software development relies on various tools - compilers, simulators, execution time estimators - that encapsulate a more-or-less detailed knowledge of the target hardware platform. These tools can be costly to develop and maintain:significant benefits could be expected if they were automatically generated from models expressed in a dedicated modeling language.In contrast with Hardware Description Languages (HDLs), that focus on the internal structure and behavior of an electronic board of chip, Hardware Architecture Description Languages consider hardware as a platform for software execution. Such a platform will be described in terms of low-level programming interface (processor instruction set),resources (processing elements, memory and peripheral devices) and elementary services (arithmetic and logic operations, bus transactions).This paper gives an overview of HARMLESS (Hardware ARchitecture Modeling Language for Embedded Software Simulation), a new domain-specific language for modeling embedded hardware platforms. HARMLESS and its associated tools follow the Model-Driven Engineering philosophy: metamodeling and model transformations have been successfully applied to the automatic generation of processor simulators

An Architecture Description Language for Embedded Hardware Platforms

Embedded software development relies on various tools - compilers, simulators, execution time estimators - that encapsulate a more-or-less detailed knowledge of the target hardware platform. These tools can be costly to develop and maintain:significant benefits could be expected if they were automatically generated from models expressed in a dedicated modeling language.In contrast with Hardware Description Languages (HDLs), that focus on the internal structure and behavior of an electronic board of chip, Hardware Architecture Description Languages consider hardware as a platform for software execution. Such a platform will be described in terms of low-level programming interface (processor instruction set),resources (processing elements, memory and peripheral devices) and elementary services (arithmetic and logic operations, bus transactions).This paper gives an overview of HARMLESS (Hardware ARchitecture Modeling Language for Embedded Software Simulation), a new domain-specific language for modeling embedded hardware platforms. HARMLESS and its associated tools follow the Model-Driven Engineering philosophy: metamodeling and model transformations have been successfully applied to the automatic generation of processor simulators

Harmless, a Hardware Architecture Description Language Dedicated to Real-Time Embedded System Simulation

International audienceValidation and Verification of embedded systems through simulation can be conducted at many levels, from the simulation of a high-level application model to the simulation of the actual binary code using an accurate model of the processor. However, for real-time applications, the simulated execution time must be as close as possible to the execution time on the actual platform and in this case the latter gives the closest results. The main drawback of the simulation of application's software using an accurate model of the processor resides in the development of a handwritten simulator which is a difficult and tedious task. This paper presents Harmless, a hardware Architecture Description Language (ADL) that mainly targets real-time embedded systems. Harmless is dedicated to the generation of simulator of the hardware platform to develop and test real-time embedded applications. Compared to existing ADLs, Harmless1) offers a more flexible description of the Instruction Set Architecture (ISA) 2) allows to describe the microarchitecture independently of the ISA to ease its reuse and 3) compares favorably to simulators generated by the existing ADLs toolsets

Composants virtuels comportementaux pour applications de compression d'images

Afin de faire face aux nouveaux besoins des applications d'imagerie numérique et au volume croissant de données qu'elles manipulent, des techniques de compression de plus en plus élaborées sont requises, donnant naissance à de nouveaux standards tels que le tout récent JPEG2000 pour le codage des images fixes. Dans cet article, nous nous intéressons à l'implantation sur architecture matérielle d'une chaîne de compression d'images à base de composants virtuels réutilisables. Face à la complexité des algorithmes à implanter et à la variété des profils d'applications supportés par JPEG2000, les méthodes traditionnelles de conception au niveau RTL trouvent leurs limites, c'est pourquoi nous proposons de rehausser le niveau d'abstraction de la spécification et de bénéficier des nouveaux outils de synthèse d'architecture du commerce afin d'introduire la notion de flexibilité architecturale d'un composant virtuel. Nous présentons ici l'application de notre méthodologie, développée dans le cadre du projet RNRT MILPAT, à la conception d'un composant virtuel de haut niveau pour la transformation en ondelettes discrète bidimensionnelle

Méthodologie de conception de composants virtuels comportementaux pour une chaîne de traitement du signal embarquée

Future satellites for earth observation will have to fulfill growing needs in image resolution, precision and quality. New image compression techniques are needed in order to overcome the heavy cost of storage device and the limited communication bandwidths : among the considered techniques, the JPEG2000 standard offers a promising compression scheme. The increasing complexity of applications and technologies, together with the heavy integration constraints - small dimensions, low power consumption, radiation tolerance, real-time data processing - sets a challenge to the design and verification methodologies for onboard embedded systems. Current trends consider raising the abstraction level of system specification and reusing pre-designed, pre-verified hardware components known as virtual components, or Intellectual Property (IP) cores. We propose a new methodology for virtual component design targeting signal and image processing applications. Our approach aims at providing a framework for designing and synthesizing highly flexible IP cores through behavioral-level specification and High-Level Synthesis tools. Our methodology has been applied to the design of a Discrete Wavelet Transform virtual component for JPEG2000 image compression.Les futures générations de satellites d'observation de la Terre doivent concilier des besoins croissants en résolution, précision et qualité des images avec un coût élevé de stockage des données à bord et une bande passante limitée des canaux de transmission. Ces contraintes imposent de recourir à de nouvelles techniques de compression des images parmi lesquelles le standard JPEG2000 est un candidat prometteur. Face à la complexité croissante des applications et des technologies, et aux fortes contraintes d'intégration - faible encombrement, faible consommation, tolérance aux radiations, traitement des informations en temps réel - les outils et méthodologies de conception et de vérification classiques apparaissent inadaptés à la réalisation des systèmes embarqués dans des délais raisonnables. Les nouvelles approches envisagées reposent sur une élévation du niveau d'abstraction de la spécification d'un système et sur la réutilisation de composants matériels pré-définis et pré-vérifiés (composants virtuels , ou blocs IP pour Intellectual Property). Dans cette thèse, nous nous intéressons à la conception de composants matériels réutilisables pour des applications intégrant des fonctions de traitement du signal et de l'image. Notre travail a ainsi consisté à définir une méthodologie de conception de composants virtuels hautement flexibles décrits au niveau comportemental et orientés vers les outils de synthèse de haut niveau. Nous avons expérimenté notre méthodologie sur l'implantation sous forme d'un composant virtuel comportemental d'un algorithme de transformation en ondelettes bidimensionnelle pour la compression d'images au format JPEG2000

Design of a Flexible 2-D Discrete Wavelet Transform IP Core for JPEG2000 Image Coding in Embedded Imaging Systems

International audienceThe increasingly demanding requirements of multimedia applications have led to the definition of complex image and video coding standards such as JPEG2000 and MPEG4. Implementation of image or video encoders or decoders on mobile device requires high integration densities together with an ability for "real-time" (on-the-fly) data processing. Today, the electronic system design community is mainly concerned with defining efficient System-on-a-Chip (SoC) design methodologies in order to benefit from the high integration capabilities of current ASIC and FPGA technologies on the one hand, and manage the increasing algorithmic complexity of applications on the other hand. Intellectual Property (IP) reuse is considered as the key to speed up the system design and verification flow and make it more reliable. In this context, we have introduced a novel methodology for VLSI implementation of computation-intensive algorithms targeting digital signal processing applications. Our methodology combines Intellectual Property (IP) reuse and High-Level Synthesis (HLS) and introduces the notion of "Behavioral IP". This approach aims at leveraging IP re-usability through functional and architectural flexibility based on: (1) modeling a component's behavior at a high abstraction level and (2) benefiting from HLS tools for architectural exploration and hardware generation

A Methodology for Behavioral Virtual Component Specification Targeting SoC Design with High-Level Synthesis Tools

While SoC design and Virtual Component (VC) reuse are on their way to becoming unavoidable practices, it is well known that the increasing complexity of applications and of VCs themselves will soon require new methodologies from the side of VC providers as well as system integrators. Designing faster and providing generic and cost-effective components will require raising the abstraction level and benefit from higher-level integration tools. High-Level Synthesis (HLS) is a promising approach to quickly generate RTL architectures from a behavioral description [1][2]. Describing hardware at such a high level is not obvious, and distributing behavioral VCs may seem all the more hazardous since all commercial tools do not support a common language syntax and semantic model. In this paper, we propose a design guidance method based on tying a tool-independent functional description of a VC to a hierarchical finite-state machine model. This approach ensures correctness of the initial description with respect to semantic properties required for HLS. Starting from this model, timing and I/O constraints can be derived in a very straightforward way in order to optimize re-synthesis of the VC by the system integrator. Then the optimized tool-independent model of a VC can be translated towards a target HLS tool by applying systematic, tool-specific writing style transformation rules

Retour d’expérience sur l’utilisation déclarative d’un langage de transformation pour la génération de code : de AADL vers OSEK/VDX OS

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